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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
DALLAS SEMICONDUCTOR
DS3150 3.3V T3 / E3 / STS-1 Line Interface
Preliminary Data Sheet Version 1 August 20, 1999
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
REVISION HISTORY
Version 1 (8/20/99) Original release.
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
TABLE OF CONTENTS
Section 1: Functional Description .................................................................................. Section 2: Signal Description....................................................................................... Section 3: AC Characteristics....................................................................................... Section 4: Mechanical Dimensions................................................................................ Section 5: Applications...............................................................................................
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
SECTION 1: FUNCTIONAL DESCRIPTION
The DS3150 performs all of the functions necessary for interfacing at the physical layer to T3, E3, and STS1 lines. The device has independent receive and transmit paths. See Figure 1A. The receiver performs clock and data recovery and monitors for the loss of the incoming signal. The recovered data can be B3ZS/HDB3 decoded and output in a NRZ format. The transmitter accepts either NRZ or bipolar data and will create the waveforms that will be driven onto the T3, E3, or STS-1 COAXial (COAX) cable. Each of these sections will be discussed separately below. Table 1A lists the primary features in the DS3150. Table 1B lists the telecommunications standards that the DS3150 was designed to meet.
DS3150 Block Diagram Figure 1A
RMON (21)
MCLK (19)
LOS* (27) Output Decode PRBS/DM (12)
Digital Loss Of Signal Detector
PRBS Detector
20dB Flat Gain
RX- (3)
(Analog Loss Of Signal Detect)
Clock & Data Recovery
Jitter Attenuator (can be placed in either the receive path or the transmit path)
RX+ (1)
mux
Filter / Equalizer
B3ZS/HDB3 Decoder
RPOS/RNRZ (25) RNEG (24)
Clock Invert Remote Loopback
RCLK (23)
squelch Analog Loopback
ZCSE* (20) ICE (10) TESS (13) TNEG (15) TPOS/TNRZ (14) mux Clock Invert mux TCLK (16)
Driver Monitor
TX+ (9) Line Driver TX- (11) WaveShaping
B3ZS/ HDB3 Encoder
Loopback Control Power Connections Test Functions
AIS / 1010.../ PRBS Generation
liu_bd
TTS* (18)
LBKS* (28)
VDD (7/17/26)
VSS (6/8/22)
EFE (2)
TDS0 (4)
TDS1 (5)
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
Feature List Table 1A * * * * * * * * * * * * * * * * * * * * * * Integrated transmit & receive T3 (44.736Mbps) / E3 (34.368Mbps) / STS-1 (51.84Mbps) line interface Performs clock/data recovery & wave shaping Requires no special external components others than 1:2 transformers Interfaces to 75 ohm coaxial cable at lengths up to 380 meters (T3), 440 meters (E3), or 360 meters (STS-1) Adaptive receive equalizer handles from 0db to 15dB of cable loss Jitter attenuator that can be placed either in the receive path or the transmit path or disabled Low power 3.3V operation with 5V tolerant I/O Pin compatible to the TDK 78P7200 & 78P2241 footprint Transmit & Receive interfaces use the same transformer (1:2) Onboard B3ZS and HDB3 coder/decoder Bipolar and NRZ interfaces Analog and digital loopbacks Onboard 215 - 1 and 223 - 1 Pseudo Random Bit Sequence (PRBS) generator & detector Transmit line driver monitor that checks for a faulty transmitter or a shorted output Complete T3 AIS generator according to ANSI T1.107 Unframed all ones generator (E3 AIS) Digital clock edge control (clock inversion capability) Tri-state capable line driver which places the device into a low power mode Able to interface directly to a DSX monitor signal (20dB flat loss) Loss of signal detector per ANSI T1.231-1999 and ITU G.775 Industrial temperature operating range (-40C to +85C) Small 28-pin PLCC package
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
Applicable Standards Table 1B 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) American National Standard for Telecommunications - ANSI T1.107 - 1995 "Digital Hierarchy - Formats Specification" American National Standard for Telecommunications - ANSI T1.231 - 199X - Draft "Digital Hierarchy Layer 1 In-Service Digital Transmission Performance Monitoring" American National Standard for Telecommunications - ANSI T1.231 - 1993 "Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring" American National Standard for Telecommunications - ANSI T1.404 - 1994 "Network-to-Customer Installation - DS3 Metallic Interface Specification" American National Standard for Telecommunications - ANSI T1.102 - 1993 "Digital Hierarchy - Electrical Interfaces" Bellcore - GR-499-CORE, Issue 1, December 1995 "Transport Systems Generic Requirements (TSGR): Common Requirements" Bellcore - GR-253-CORE, Issue 2, December 1995 "SONET Transport Systems: Common Generic Criteria" International Telecommunication Union (ITU) G.703, 1991 "Physical/Electrical Characteristics of Hierarchical Digital Interfaces International Telecommunication Union (ITU) G.823, March 1993 "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy" International Telecommunication Union (ITU) G.775, November 1994 "Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria" International Telecommunication Union (ITU) O.151, October 1992 "Error Performance Measuring Equipment Operating at the Primary Rate and Above" European Telecommunications Standards Institute (ETSI) TBR 24, July 1997 "Business TeleCommunications; 34Mbit/s digital unstructured and structured lease lines; attachment requirements for terminal equipment interface European Telecommunications Standards Institute (ETSI) ETS 300 687, March 1996 "Business TeleCommunications; 34Mbit/s digital leased lines (D34U and D34S); Connection characteristics European Telecommunications Standards Institute (ETSI) ETS 300 686, March 1996 "Business TeleCommunications; 34Mbit/s and 140Mbits/s digital leased lines (D34U, D34S, D140U and D140S); Network interface presentation
Receiver The DS3150 interfaces to the receive T3/E3/STS-1 COAX line via a 1:2 step up transformer. See Figure 1B. The receiver automatically adapts to COAX cable loses from 0 to 15dB which translates into 0 to 380 meters (T3) or 440 meters (E3) or 360 meters (STS-1) of COAX cable (AT&T 734A or equivalent). The receiver has the ability to interface to monitor jacks as well. Via the RMON input (see Table 2A), the device can be configured to insert a 20dB flat boost into the incoming signal. Monitor jacks typically have series resistors that result in a resistive loss of 20dB. The receiver has excellent jitter tolerance characteristics. See Figure 1C. The receiver contains both analog and a digital loss of signal detectors. The analog loss of signal detector resides in the equalizer. If the incoming signal drops below -24dB of the nominal signal level, the analog loss of signal detector will activate and it will squelch the recovered data and force all zeros out of the data recovery circuitry. The analog loss of signal detector will not clear until the signal level is above -18dB of the nominal signal level. The digital Loss Of Signal (LOS) detector is activated when it detects 192 consecutive zeros. LOS is cleared when there are no Excessive Zero occurrences over a span of 192 clock periods. An Excessive Zero occurrence is defined as 3 or more consecutive zeros in the T3 & STS-1 modes and 4 or more zeros in the E3 mode. The status of the digital LOS is reflected at the LOS* output (see Table 2A). There is no status output available for the analog loss of signal detector. While the device is in a loss of signal state, the RCLK output will be referenced to the MCLK input (or the TCLK input if MCLK is tied low). The analog loss of signal detector has a longer time constant than the digital LOS. Hence when the incoming signal is lost, the digital LOS will fire first followed by the analog loss of signal detector. When a signal is restored, the digital LOS will not be allowed to qualify a signal for no Excessive Zero violations until the analog loss of signal detector has seen the signal rise above -18dB. Governing specifications for the loss of signal detectors is ANSI T1.231 and ITU G.775.
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
The recovered data from the receiver can be output in either it's native form (which is a bipolar format) or a Non Return to Zero (NRZ) format. To select the bipolar format, the ZCSE* input is tied high. In this format, the B3ZS/HDB3 decoder is disabled and the raw data as recovered is buffered and then output on the RPOS and RNEG outputs. To select the NRZ format, the ZCSE* input is tied low. In this format, the B3ZS/HBD3 decoder is enabled and the recovered data is B3ZS/HBD3 decoded and then logically OR'ed together and output at the RPOS output while the RNEG output is forced low. DS3150 External Connection Figure 1B
Transmit
0.1uF
DS3150
TX+ VDD VDD
0.1uF 1uF 10uF 0.1uF 1uF 10uF
0.05uF
330 (1%)
3.3V Power Plane
TX1:2ct
VDD
0.1uF 1uF 10uF
Receive RX+
330 (1%)
VSS VSS
0.05uF
Ground Plane
RX1:2ct
VSS
DS3150 Jitter Tolerance Figure 1C
10
T3 [GR-499 (1995)] Category II
10 5
Jitter Tolerance (UIpp)
1.0
T3 [GR-499 (1995)] Category I E3 [G.823(1993)] 1.5
DS3150 Jitter Tolerance
0.3 0.15 0.1 0.1
669 10 100 1K
2.3K 10K
22.3K
60K 100K
300K 800K 1M
Frequency (Hz)
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
Transmitter Via the ZCSE* input, the device is configured to accept either bipolar data or NRZ data to be input to the transmitter. When the ZCSE* input is tied high, bipolar data must be applied at the TPOS and TNEG inputs. In this mode, the device will not B3ZS/HDB3 encode the outgoing data stream. When the ZCSE* input is tied low, a NRZ data stream must be applied at the TPOS input (TNEG is ignored). In this mode, the device will B3ZS/HDB3 encode the outgoing data stream. The clock applied at the TCLK input is used to transmit data out onto the T3/E3/STS-1 line. Hence TCLK must be of transmission quality (i.e. accurate to 20ppm). The duty cycle of TCLK is not a key parameter as long as the clock high and low times listed in Section 3 are met. The DS3150 also has ability to generate a number of different patterns. It can generate either an unframed all ones pattern (which is also the E3 AIS signal), a 101010... pattern, or a T3 Alarm Indication Signal (AIS). See Figure 1E for a description of the T3 AIS. The TDS0 and TDS1 inputs are used to select these onboard patterns. See Tables 2A and 2B. The DS3150 interfaces to the transmit T3/E3/STS-1 COAX cable via a 1:2 step up transformer. See Figure 1B. It will drive the 75 ohm cable and create the proper waveforms required for interfacing to T3/E3/STS-1 lines. Tables 1C through 1G and Figure 1D detail the waveform template specifications and testing parameters. The transmitter can be disabled and the TX+ and TX- outputs tri-stated via the TTS* input. See Table 2A for details. The transmit driver monitor constantly checks the analog signal output at TX+ and TX-. If the output fails, then the PRBS/DM output will be forced to source an inverted RCLK. See Figures 1F and 1G. When the transmitter is disabled (TTS* = 0), the driver monitor is also disabled. T3 Transmit Waveform Template Table 1C Time Axis Range Normalized Amplitude Equations Upper Curve 0.03 -0.85 T -0.68 -0.68 T 0.36 0.5 {1 + sin[(/2)(1 + T/0.34)]} + 0.03 0.08 + 0.407e-1.84(T - 0.36) 0.36 T 1.4 Lower Curve -0.03 -0.85 T -0.36 -0.36 T 0.36 0.5 {1 + sin[(/2)(1 + T/0.18)]} - 0.03 -0.03 0.36 T 1.4 Governing Specifications: ANSI T1.102-1993 and Bellcore GR-499.
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
T3 Transmit Waveform Test Parameters and Limits Table 1D Parameter Rate Line code Transmission medium Test measurement point Test termination Pulse amplitude Pulse shape Specification 44.736Mbit/s ( 20 ppm) B3ZS COAX cable (AT&T 734A or equivalent) At the end of 0 to 450 feet of COAX cable 75 ohms ( 1%) resistive Between 0.36V and 0.85V An isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the curved listed in Table 1C Between -1.8dBm and +5.7dBm At least 20dB less than the power measured at 22.368MHz Ratio of positive and negative pulses must be between 0.90 and 1.10
Unframed All Ones Power level @ 22.368MHz Unframed All Ones Power level @ 44.736MHz Pulse imbalance of isolated pulses
STS-1 Transmit Waveform Template Table 1E Time Axis Range Normalized Amplitude Equations Upper Curve 0.03 -0.85 T -0.68 -0.68 T 0.26 0.5 {1 + sin[(/2)(1 + T/0.34)]} + 0.03 0.1 + 0.61e-2.4(T - 0.26) 0.26 T 1.4 Lower Curve -0.03 -0.85 T -0.36 -0.36 T 0.36 0.5 {1 + sin[(/2)(1 + T/0.18)]} - 0.03 -0.03 0.36 T 1.4 Governing Specifications: Bellcore GR-253 and Bellcore GR-499.
STS-1 Transmit Waveform Test Parameters and Limits Table 1F Parameter Rate Line code Transmission medium Test measurement point Test termination Pulse shape Specification 51.840Mbit/s ( 20 ppm) B3ZS COAX cable (AT&T 734A or equivalent) At the end of 0 to 450 feet of COAX cable 75 ohms ( 1%) resistive An isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the curved listed in Table 1E Between -1.8dBm and +5.7dBm At least 20dB less than the power measured at 25.92MHz
Unframed All Ones Power level @ 25.92MHz Unframed All Ones Power level @ 51.84MHz
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
E3 Transmit Waveform Template Figure 1D 1.2 1.1 1.0 0.9 0.8 0.7
17ns
8.65ns G.703 E3 Template 12.1ns
Output 0.6 Level (V)
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
24.5ns 29.1ns
Time (ns)
E3 Transmit Waveform Test Parameters and Limits Table 1G Parameter Rate Line code Transmission medium Test measurement point Test termination Pulse amplitude Pulse shape Specification 34.368Mbit/s ( 20 ppm) HDB3 COAX cable (AT&T 734A or equivalent) At the transmitter 75 ohms ( 1%) resistive 1.0V (nominal) An isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the template shown in Figure 1D 0.95 to 1.05 0.95 to 1.05
Ratio of the amplitudes of positive and negative pulses at the center of the pulse interval Ratio of the widths of positive and negative pulses at the nominal half amplitude
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
T3 AIS Structure Figure 1E M1 Subframe
X1 (1) 84 Info Bits F1 (1) 84 Info Bits C1 (0) 84 Info Bits F2 (0) 84 Info Bits C2 (0) 84 Info Bits F3 (0) 84 Info Bits C3 (0) 84 Info Bits F4 (1) 84 Info Bits
M2 Subframe
X2 (1) 84 Info Bits F1 (1) 84 Info Bits C1 (0) 84 Info Bits F2 (0) 84 Info Bits C2 (0) 84 Info Bits F3 (0) 84 Info Bits C3 (0) 84 Info Bits F4 (1) 84 Info Bits
M3 Subframe
P1 (0) 84 Info Bits F1 (1) 84 Info Bits C1 (0) 84 Info Bits F2 (0) 84 Info Bits C2 (0) 84 Info Bits F3 (0) 84 Info Bits C3 (0) 84 Info Bits F4 (1) 84 Info Bits
M4 Subframe
P2 (0) 84 Info Bits F1 (1) 84 Info Bits C1 (0) 84 Info Bits F2 (0) 84 Info Bits C2 (0) 84 Info Bits F3 (0) 84 Info Bits C3 (0) 84 Info Bits F4 (1) 84 Info Bits
M5 Subframe
M1 (0) 84 Info Bits F1 (1) 84 Info Bits C1 (0) 84 Info Bits F2 (0) 84 Info Bits C2 (0) 84 Info Bits F3 (0) 84 Info Bits C3 (0) 84 Info Bits F4 (1) 84 Info Bits
M6 Subframe
M2 (1) 84 Info Bits F1 (1) 84 Info Bits C1 (0) 84 Info Bits F2 (0) 84 Info Bits C2 (0) 84 Info Bits F3 (0) 84 Info Bits C3 (0) 84 Info Bits F4 (1) 84 Info Bits
M7 Subframe
M3 (0) 84 Info Bits F1 (1) 84 Info Bits C1 (0) 84 Info Bits F2 (0) 84 Info Bits C2 (0) 84 Info Bits F3 (0) 84 Info Bits C3 (0) 84 Info Bits F4 (1) 84 Info Bits
Notes: 1. X1 is transmitted first. 2. The 84 Info Bits are the sequence 101010... where the one ("1") starts after each X, P, F, C, or M bit.
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DS3150 Preliminary Data Sheet (V1)
August 20, 1999
Diagnostics The DS3150 contains an onboard Pseudo Random Binary Sequence (PRBS) generator and detector. This function is useful in testing the device at the physical layer. It will generate and detect either a 215 - 1 (T1 or STS-1) or 223 - 1 PRBS according to the ITU O.151 specification. The PRBS pattern generated and detected by the DS3150 is an unframed pattern. In other words, no T3, E3, or STS-1 framing patterns are inserted in the transmit data stream nor expected in the received data stream. The PRBS generator is enabled via the TDS0 and TDS1 inputs. See Tables 2A and 2B for details. The PRBS detector is always enabled and will report it's status via the PRBS/DM output. When the PRBS detector is out of synchronization, the PRBS/DM output will be forced high. When the PRBS detector synchronizes to the incoming pseudorandom pattern, the PRBS/DM output will go low and then pulse high for each bit detected in error. The status of the PRBS detector is overridden when the transmitter driver monitor detects a faulty transmitter. When this occurs, the PRBS/DM will source an inverted RCLK regardless of the current state of the PRBS detector. See Figures 1F and 1G. On the receive side, the recovered data is B3ZS/HDB3 decoded before it is routed to the PRBS decoder. The DS3150 also has two internal loopbacks that can be used for testing. See Figure 1A. The Analog Loopback loops the outgoing transmit waveform back to the receiver. When this loopback is enabled, data will be transmitted as it normally would be and the incoming data at RX+ and RX- is ignored. The Remote Loopback loops data from the receive side to the transmit side. When this loopback is enabled, data will continue to pass through the receive side as it normally would and data at the TPOS and TNEG inputs is ignored. These two loopbacks are invoked via the LBKS* input. See Table 2A.
PRBS/DM Output With Normal RCLK Operation (ICE = 0 or 1) Figure 1F
RCLK
PRBS/DM PRBS Detector is Not in Sync
PRBS Detector is In Sync; the PRBS/DM Signal Will Pulse High for Each Bit Error Detected
If Transmit Driver Monitor Senses that the Transmitter Has Failed, the PRBS/DM Signal Will Output An Inverted RCLK
PRBS/DM Output With Inverted RCLK Operation (ICE = Float) Figure 1G
RCLK
PRBS/DM
PRBS Detector is Not in Sync
PRBS Detector is In Sync; the PRBS/DM Signal Will Pulse High for Each Bit Error Detected
If Transmit Driver Monitor Senses that the Transmitter Has Failed, the PRBS/DM Signal Will Output An Inverted RCLK
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
Jitter Attenuator The DS3150 contains an onboard jitter attenuator that can be placed in either the receive path or the transmit path or disabled. This selection is made via the RMON and TTS* input signals. See Table 1H below for details. Figure 1H shows the minimum jitter attenuation for the device when the jitter attenuator is enabled. Figure 1H also shows the receive jitter transfer when the jitter attenuator is disabled. Depending on whether the device is in the T3/STS-1 or E3 mode, the jitter attenuation will be adjusted. RMON & TTS* Signal Decode Table 1H RMON 0 0 0 1 1 1 Float Float Float TTS* 0 1 Float 0 1 Float 0 1 Float Receive 20dB Flat Gain disabled disabled disabled enabled enabled enabled disabled disabled disabled Transmit Line Driver tri-stated enabled enabled tri-stated enabled enabled tri-stated enabled enabled Jitter Attenuator disabled disabled enabled in TX path disabled disabled enabled in TX path enabled in RX path enabled in RX path enabled in RX path
DS3150 Jitter Attenuation / Jitter Transfer Figure 1H
17Hz 0 T3 [GR-499 (1995)] 800 60K
E3 [TBR24 (1997)]
-10
Jitter Attenuation (dB)
-20
DS3150 E3 Minimum Jitter Attenuation
DS3150 T3 / STS-1 Minimum Jitter Attenuation
DS3150 Typical Receiver Jitter Transfer with Jitter Attenuation Disabled
-30
15K 10 100 1K 10K 100K 1M
Frequency (Hz)
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
SECTION 2: SIGNAL DESCRIPTION
Table 2A below lists all of the signals on the DS3150 and their function. The signals are listed in order by their pin number. Signal Descriptions Table 2A Pin 1 2 Signal Name RX+ EFE I/O I I3 Description Receive Analog Input. This analog input is coupled to the T3, STS-1, or E3 75 COAX line via a 1:2 step-up transformer. See Figure 1B for details. Enhanced Feature & Test Mode Enable. This signal selects whether the enhanced features (ability to transmit all ones, T3 AIS, or a 1010... pattern and PRBS generation/detection and the transmit driver monitor) are enabled or not. 0 = Enhanced Features Disabled: pins 4 & 5 are ignored and pin 12 is tri-stated. 1 = Enhanced Features Enabled: pins 4 & 5 are active and defined as TDS0 & TDS1 respectively and pin 12 is active and defined as PRBS/DM. FLOAT = Test Mode Enabled: pins 4, 5, 12 & 27 are redefined as test pins. Receive Analog Input. This analog input is coupled to the T3, STS-1, or E3 75 COAX line via a 1:2 step-up transformer. See Figure 1B for details. Transmit Data Select Bit 0. This signal selects the source of the transmit data. See Table 2B. If EFE is set low, then this signal is ignored. Transmit Data Select Bit 1. This signal selects the source of the transmit data. See Table 2B. If EFE is set low, then this signal is ignored. Ground Reference. All VSS signals should be tied together. Positive Supply. 3.3V 5%. All VDD signals should be tied together. Ground Reference. All VSS signals should be tied together. Transmit Analog Output. This analog output drives the T3, STS-1, or E3 signal into the 75 COAX line. This signal is connected via a 2:1 step-down transformer to the COAX line. See Section 1 for details. This output can be tri-stated via the TTS* input signal. Invert Clock Enable. This signal determines on which RCLK edge RPOS/RNEG is updated and which TCLK edge TPOS/TNEG is sampled. 0 = Normal RCLK / Normal TCLK: update RPOS/RNEG on falling edge of RCLK and sample TPOS/TNEG on rising edge of TCLK 1 = Normal RCLK / Inverted TCLK: update RPOS/RNEG on falling edge of RCLK and sample TPOS/TNEG on falling edge of TCLK FLOAT = Inverted RCLK / Inverted TCLK: update RPOS/RNEG on rising edge of RCLK and sample TPOS/TNEG on falling edge of TCLK Transmit Analog Output. This analog output drives the T3, STS-1, or E3 signal into the 75 COAX line. This signal is connected via a 2:1 step-down transformer to the COAX line. See Section 1 for details. This output can be tri-stated via the TTS* input signal. PRBS Detector and Transmit Driver Monitor Output. This signal reports the status of the PRBS detector and the Transmit Driver Monitor. The PRBS detector will constantly search for either a 215 - 1 (T3 or STS-1) or 223 - 1 pseudo random pattern. This signal will remain high when the PRBS detector is out of synchronization. When the PRBS detector synchronizes to the pseudo random pattern, then this signal will go low and will create a positive going pulse (synchronous with RCLK) for each bit error detected. If the transmit driver monitor detects a faulty transmitter, then the PRBS detector output will be overridden and this output will source an inverted RCLK. See Figures 1F and 1G for more details. If EFE is set low, then this signal is tri-stated. T3 / E3 / STS-1 Select. This input determines the mode of operation for the device. 0 = E3 1 = T3 FLOAT = STS-1
3 4 5 6 7 8 9
RXTDS0 TDS1 VSS VDD VSS TX+
I I I O3
10
ICE
I3
11
TX-
O3
12
PRBS/ DM
O3
13
TESS
I3
14
DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
Pin 14
Signal Name TPOS/ TNRZ
I/O I
Description Transmit Positive Data. If a bipolar data stream is to be transmitted, then the B3ZS/HDB3 encoder/decoder should be disabled (ZCSE* = 1) and the positive half of the bipolar data stream should be applied to TPOS and the negative half to TNEG. If a NRZ data stream is to be transmitted, then the B3ZS/HDB3 encoder/decoder should be enabled (ZCSE* = 0) and the NRZ data stream should be applied to TPOS, TNEG is ignored and can be tied either high or low. TPOS is sampled either on the falling edge of TCLK (ICE = 1 or FLOAT) or the rising edge of TCLK (ICE = 0). Transmit Negative Data. If a bipolar data stream is to be transmitted, then the B3ZS/HDB3 encoder/decoder should be disabled (ZCSE* = 1) and the positive half of the bipolar data stream should be applied to TPOS and the negative half to TNEG. If a NRZ data stream is to be transmitted, then the B3ZS/HDB3 encoder/decoder should be enabled (ZCSE* = 0) and the NRZ data stream should be applied to TPOS, TNEG is ignored and can be tied either high or low. TNEG is sampled either on the falling edge of TCLK (ICE = 1 or FLOAT) or the rising edge of TCLK (ICE = 0). Transmit Clock. Either a T3 (44.736MHz 20ppm), E3 (34.368MHz 20ppm), or STS-1 (51.84 20ppm) clock should be applied at this signal. Data to be transmitted will be clocked into the device at TPOS & TNEG either on a rising edge of TCLK (ICE = 0) or falling edge of TCLK (ICE = 1 or FLOAT). The duty cycle on TCLK is not restricted as long it meets the high and low times listed in Section 3. Positive Supply. 3.3V 5%. All VDD signals should be tied together. Transmit Tri-State Output Driver. This input determines whether the TX+ and TX- analog output signals are forced into tri-state or are active. This input also controls the jitter attenuator. See Table 2C. 0 = tri-state the transmit output driver & disable TX jitter attenuation 1 = enable transmit driver & disable TX jitter attenuation FLOAT = enable the transmit driver & enable TX jitter attenuation Master Clock. The clock input at this signal is used by the clock and data recovery machine. Either a T3 (44.736MHz 20ppm), E3 (34.368MHz 20ppm), or STS-1 (51.84 20ppm) clock should be applied at this signal. Tying this pin low forces the device to use the clock applied at the TCLK input for the receive side clock and data recovery. Zero Code Suppression Enable. 0 = B3ZS/HDB3 encoder/decoder enabled (NRZ interface enabled) 1 = B3ZS/HDB3 encoder/decoder disabled (NRZ interface disabled) Receive Monitor Mode. This input determines whether or not a 20db flat gain will be applied to the incoming signal before it is feed to the receive equalizer. This mode is invoked when the device is being used to monitor signals that have been resistively attenuated by a monitor jack. In this mode, the maximum input signal allowed at RX+ and RX- is reduced by 20dB. This input also controls the jitter attenuator. See Table 2C. 0 = disable the 20dB gain & disable RX jitter attenuation 1 = enable the 20dB gain & disable RX jitter attenuation FLOAT = disable the 20dB gain & enable RX jitter attenuation Ground Reference. All VSS signals should be tied together. Receive Clock. The recovered clock is output at the signal. When the experiences a Loss Of Signal (LOS = 0), the clock applied at MCLK (or TCLK if MCLK is tied low) appears at this signal. The recovered data is updated at the RPOS & RNEG outputs on either the falling edge of RCLK (ICE = 0 or 1) or the rising edge of RCLK (ICE = FLOAT). Receive Negative Data. When the B3ZS/HBD3 encoder/decoder is disabled (ZCSE* = 1), this signal will contain the negative half of the recovered bipolar data steam. When the B3ZS/HDB3 encoder/decoder is enabled (ZCSE* = 0), this signal will be forced low and the NRZ data stream will be output at RPOS. This signal will be updated either on the rising edge of RCLK (ICE = FLOAT) or the falling edge of RCLK (ICE = 0 or 1) with the recovered data stream.
15
TNEG
I
16
TCLK
I
17 18
VDD TTS*
I3
19
MCLK
I
20
ZCSE*
I
21
RMON
I3
22 23
VSS RCLK
O
24
RNEG
O
15
DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
Pin 25
Signal Name RPOS/ RNRZ
I/O O
Description Receive Positive or NRZ Data. When the B3ZS/HBD3 encoder/decoder is disabled (ZCSE* = 1), this signal will contain the positive half of the recovered bipolar data steam. When the B3ZS/HDB3 encoder/decoder is enabled (ZCSE* = 0), this signal will contain the recovered NRZ data stream. This signal will be updated either on the rising edge of RCLK (ICE = FLOAT) or the falling edge of RCLK (ICE = 0 or 1) with the recovered data stream. Positive Supply. 3.3V 5%. All VDD signals should be tied together. Loss Of Signal. Loss Of Signal (LOS) is an active low signal. It will be asserted upon detection of 192 consecutive zeros. Signals lower than 21db below nominal are squelched. LOS is cleared when there are no Excessive Zero occurrences over a span of 192 clock periods. An Excessive Zero occurrence is defined as 3 or more consecutive zeros in the T3 & STS-1 modes and 4 or more zeros in the E3 mode. Governing Specifications are ANSI T1.231 and ITU G.775. Loopback Select. This input determines if either the Analog Loopback or the Remote Loopback is enabled. See the Block Diagram in Section 1 for details. 0 = Analog Loopback Enabled 1 = No Loopback Enabled FLOAT = Remote Loopback Enabled
26 27
VDD LOS*
O
28
LBKS*
I3
Notes: 1. I3 is an input capable of detecting 3 states, high, low and float. 2. O3 is an output that is tri-state capable. 3. Symbols appended with an asterisks (*) are active low signals.
Transmit Data Mode Select Pin Descriptions Table 2B TDS1 0 0 1 1 1 1 TDS0 0 1 0 0 1 1 TESS X X E3 or STS-1 T3 E3 T3 or STS-1 Transmit Mode Selected Transmit data normally as input at TPOS and TNEG Transmit Unframed All Ones Transmit an Unframed 101010... pattern Transmit T3 AIS as per ANSI T1.107 (see Figure 1C) Transmit a 223 - 1 PRBS pattern as per ITU O.151 Transmit a 215 - 1 PRBS pattern as per ITU O.151
Notes: 1. TESS = 0 for E3 / TESS = 1 for T3 / TESS = float for STS-1 2. TDS0 & TDS0 are ignored when EFE is tied low and the device will transmit data as input at TPOS & TNEG
16
DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
RMON & TTS* Signal Decode Table 2C RMON 0 0 0 1 1 1 Float Float Float TTS* 0 1 Float 0 1 Float 0 1 Float Receive 20dB Flat Gain disabled disabled disabled enabled enabled enabled disabled disabled disabled Transmit Line Driver tri-stated enabled enabled tri-stated enabled enabled tri-stated enabled enabled Jitter Attenuator disabled disabled enabled in TX path disabled disabled enabled in TX path enabled in RX path enabled in RX path enabled in RX path
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DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
SECTION 3: AC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS* Voltage on Any Lead with Respect to VSS (except VDD) Supply Voltage (VDD) with Respect to VSS Operating Temperature Storage Temperature Soldering Temperature -0.3V to 5.5V -0.3V to 3.63V -40C to +85C -55C to +125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Note: the typical values listed below are not production tested. RECOMMEND DC OPERATING CONDITIONS Parameter Logic 1 Logic 0 Supply (VDD) Symbol VIH VIL VDD Min 2.4 -0.3 3.165 Typ Max 5.5 0.8 3.465 (-40C to +85C) Units V V V Notes
DC CHARACTERISTICS Parameter Supply Current @ VDD = 3.465V Power Down Current @ VDD = 3.465V Lead Capacitance Input Leakage Input Leakage (w/ pull-ups or float) Output Leakage Output Current (2.4V) Output Current (0.4V) Symbol IDD IPD CIO IIL IILP ILO IOH IOL
(-40C to +85C; VDD = 3.135V to 3.465V) Min Typ TBD TBD 7 -10 -500 -10 -4.0 +4.0 +10 +500 +10 Max Units mA mA pF uA uA uA mA mA 3 3 4 Notes 1 2
Notes: 1. TCLK = MCLK = 44.736MHz & TX+ and TX- driving all ones into a 75 ohm load / other inputs at VDD or grounded / other outputs left open circuited 2. MCLK = 44.736MHz & TTS* = 0 / other inputs at VDD or grounded / other outputs left open circuited 3. 0V < Vin < VDD 4. Outputs in Tri-State
18
DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
AC CHARACTERISTICS - Digital Parameter RCLK / TCLK Clock Period Symbol t1 t1 t1 t2 / t3 t2 / t3 t2 / t3 t2 / t3 t4 t5 t6 9.0 11.6 7.7 7 2 2 2 6 (-40C to +85C; VDD = 3.135V to 3.465V) Min Typ Max Units Notes 22.4 29.1 19.3 11.2 14.5 9.6 13.4 17.4 11.5 ns ns ns ns ns ns ns ns ns ns 4,5 1 2 3 1 2 3
RCLK Clock High / Low Time
TCLK Clock High / Low Time TPOS or TNEG Set Up Time to the Falling Edge or Rising Edge of TCLK TPOS or TNEG Hold Time from the Falling Edge or Rising Edge of TCLK Delay from the Rising Edge or Falling Edge of RCLK to Data Valid on RPOS or RNEG or Signal Change on PRBS/DM
Notes: 1. T3 Mode 2. E3 Mode 3. STS-1 Mode 4. In Normal Mode, TPOS and TNEG are sampled on the rising edge of TCLK and RPOS and RNEG are updated on the falling edge of RCLK 5. In Inverted Mode, TPOS and TNEG are sampled on the falling edge of TCLK and RPOS and RNEG are updated on the rising edge of RCLK AC TIMING DIAGRAM Figure 3A
t1 t2 RCLK (normal mode) / TCLK (inverted mode) TCLK (normal mode) / RCLK (inverted mode) t4 TPOS / TNEG t6 RPOS / RNEG / PRBS/DM
ac_tim
t3
t5
19
DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
SECTION 4: MECHANICAL DIMENSIONS
20
DALLAS SEMICONDUCTOR
DS3150 Preliminary Data Sheet (V1)
August 20, 1999
SECTION 5: APPLICATIONS
Channelized T3/E3 Application Figure 5A
8.192MHz I/F
PCI Bus
DS3134 CHATEAU 256 Channel HDLC Controller
8.192MHz I/F
DS3120/ DS3124 28/21 Channel T1/E1 Framer
T1/E1 data streams
DS3112 TEMPE T3/E3 Framer & M13/ E13/ G747 Mux
bipolar I/F
DS3150 T3/E3 Line Interface
T3/E3 Line
Dual Unchannelized T3/E3 Application Figure 5B
DS3112 TEMPE
44.2Mbps (T3) or 34Mbps (E3) datastream
PCI Bus
DS3134 CHATEAU 256 Channel HDLC Controller
44.2Mbps (T3) or 34Mbps (E3) datastream
T3/E3 Framer & M13/ E13/ G747 Mux
bipolar I/F
DS3150 T3/E3 Line Interface
T3/E3 Line
DS3112 TEMPE T3/E3 Framer & M13/ E13/ G747 Mux
bipolar I/F
DS3150 T3/E3 Line Interface
T3/E3 Line
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